1. Field of the Invention
The present invention relates to a probe card suitable for electrically testing a plurality of chips formed in a form of a matrix on a semiconductor wafer.
2. Prior Art
In general, there are formed a plurality of integrated circuit portions, i.e., IC chip portions (referred to merely as a chip or chips hereinafter) in a form of a matrix on a semiconductor wafer. Each chip has a rectangular shape, and each of its edge portions corresponding to each side of the rectangular chip has a plurality of electrode pads or an electrode portion. Chips constituting rows and columns of the matrix are aligned in every row and column.
Chips of this kind are subject to the electrical test for determining whether or not the circuit formed on each chip can operate in such a manner as defined in the specification thereof. Such an electrical test is often carried out, before separating chips in pieces from the wafer, that is, in the state that the chips stay on the wafer, by means of a probe card including a plurality of probes for pressing the electrode portion with their needle point. In the electrical test of this kind, if the test is performed on the chip by chip basis, it would take a very long time to complete the test of all the chips.
In order to obviate such a long and unnecessary time consuming work, there has been proposed a probe card which enables a predetermined number of chips on the wafer to be tested in one test. In order to perform the test using such probe card, the chips lying on the wafer are first divided into groups including some chips, for instance, a group consisting of some chips which are selected every other chip or every third chips lying on the wafer, or a series of chips aligned in the form of row or column on the wafer. Then, the test is carried out on such chip groups on the group by group basis, thereby reducing the number of tests needed for completing the test of all the chips on the wafer and shortening the time required for completing the same.
In case of the above-mentioned prior art probe card, however, since the chip group which can be tested simultaneously consists of chips selected every other chip or every third chip, or a series of chips aligned in the form of row or column, it is not possible to test simultaneously four chips arranged side by side across each of the imaginary boundary lines intersecting each other substantially in the cross-like shape, in other words, four chips located around the intersection of boundary lines. Accordingly, the number of electrical tests per wafer becomes large, and it takes a long time for completing the test of one wafer.
A probe card capable of testing adjacent four chips simultaneously has been disclosed by the Japanese Patent Application Public Disclosure (KOKAI) No. H9-283575. In this probe card, the same number of probes as the number of a lot of chips are fitted to a plurality of long supporters, and these supporters are arranged on the printed circuit board in a lattice-like form.
However, according to the probe card as described above, since a lot of probes have to be fitted to each supporter, the work for fitting the probes to the supporter are apt to become complicated. Especially, should there exist only one probe erroneously fitted to the supporter, the supporter itself will be rejected through the product inspection, thus worsening the production yield of the supporter and the probe, which in turn results in the rise in their manufacturing cost. Accordingly, it is required that the work for fitting the probes to the supporter be carried out more carefully.
Therefore, in the probe card for use in the test of chips formed on the semiconductor wafer, it is the most important thing that, while adjacent four chips located around the intersection portion of the boundary lines intersecting each other in the cross-like shape can be tested simultaneously, the work for putting probe blocks together in the lattice-like form should be facilitated.